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as1160/as1161 20mhz - 66mhz, 10-bit bus, ieee 1149.1 (jtag) compliant lvds serializer/deserializer www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 1 - 29 datasheet 1 general description the as1160 (serializer) is designed to convert 10-bit wide parallel lvcmos/lvttl data bus signals into a single high-speed lvds serial data stream with clock. the as1161 (deserializer) transforms the high-speed lvds serial data stream back into a 10-bit wide parallel data bus with recovered parallel clock. both devices are compliant with ieee 1149.1 standard test access port and boundary scan architecture (including the defined boundary-scan test logic and test access port consisting of test data input, test data out, and test mode select, test clock, and test reset). the devices also feature an at-speed bist mode which allows the interconnects between the serializer and deserializer to be verified at-speed. the single differential-pair data-path makes pcb design easier, and reduced cable/pcb-trace count and connec- tor size significantly reduce cost. since one output trans- mits clock and data bits serially, clock-to-data and data- to-data skew are eliminated. powerdown mode reduces supply current when both devices are idle. both devices are available in a ctbga 49-bumps pin package. figure 1. block diagrams 2 key features serial bus lvds data rate: 660 mbps @ 66mhz clock 10-bit parallel interface synchronization mode and lock indicator programmable edge trigger on clock high impedance on rx inputs during poweroff bus lvds serial output load: 28 ieee 1149.1 (jtag) comp liant and at -speed bist te s t m o d e clock recovery from pl l lock to random data patterns guaranteed transition each data transfer cycle chipset (tx + rx) power consumption: < 500 mw @ 66mhz single differential-pair eliminates multi-channel skew flow-through pinout for simple pcb layout small ctbga 49-bumps package 3 applications the devices are ideal for cellular phone base stations, add drop muxes, digital cross-connects. dslams, net- workswitches and routers or backplane interconnect. as1160 do+ do- tclk tckr/fn input latch pll din0:9 parallel- to-serial 10 timing & control den sync1 sync2 tdi tdo tck tms ieee 1149.1 test access port trstn as1161 ri+ ri- output latch pll rout0:9 parallel- to-serial 10 timing & control refclk ren lockn rclk clock recovery rckr/fn lvds tdi tdo tck tms ieee 1149.1 test access port trstn
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 2 - 29 as1160/as1161 datasheet contents 1 general description......................................................................................................... ..................... 1 2 key features ................................................................................................................ ........................ 1 3 applications ................................................................................................................ .......................... 1 contents ....................................................................................................................... ........................................ 2 4 pinout ...................................................................................................................... ............................. 3 pin assignments and descriptions ... ............................................................................................ ........................ 3 5 absolute maximum ratings... ................................................................................................. .............. 5 6 electrical characteristics .................................................................................................. .................... 6 serializer timing requirements for tclk ....................................................................................... ................ 6 serializer switching characteristics .................. ........................................................................ ...................... 6 deserializer electrical characteri stics ....................................................................................... .......................7 deserializer timing requirements for refclk............ .............. .............. ........... ............ ........... .......... .......... 8 deserializer switching characterist ics ......................................................................................... ................... 8 scan circuitry timing requirements........................ ..................................................................... .................. 9 7 typical operating characteristics as1160 ......... ........................................................................... ..... 10 8 typical operating characteristics as1161 ...... .............................................................................. ...... 11 9 timing diagrams ............................................................................................................. .................... 12 10 detailed description ....................................................................................................... ................... 19 initialization ........................ ......................................................................................... ........................................19 data transfer.................................................................................................................. .................................... 20 resynchronization .............................................................................................................. ................................ 21 powerdown...................................................................................................................... ................................... 21 tri-state ...................................................................................................................... ........................................ 21 11 application information .. .................................................................................................. ............. 22 power considerations ........................................................................................................... ............................. 22 powering up the deserializer ........ ........................................................................................... .......................... 22 transmitting data .............................................................................................................. ................................. 22 noise margin ................................................................................................................... ................................... 23 lock loss recovery ............................................................................................................. .............................. 23 hot insertion .................................................................................................................. ..................................... 23 pcb considerations ............................................................................................................. .............................. 24 transmission media ............................................................................................................. .............................. 24 failsafe biasing ............................................................................................................... ................................... 25 signal integrity............................................................................................................... ..................................... 25 jtag test modes ................................................................................................................ ............................... 26 sample/preload ................................................................................................................. ..................... 26 bypass............. .............. .............. .............. .............. .............. .............. .............. .......... ................................ 26 extest ......................................................................................................................... ................................ 26 idcode ......................................................................................................................... ................................ 26 runbist ........................................................................................................................ ............................... 26 12 package drawings and markings .............................................................................................. ....... 27 13 ordering information...................................................................................................... .................. 28
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 3 - 29 as1160/as1161 datasheet - pinout 4 pinout pin assignments and descriptions figure 2. as1160 pin assignments (top view) table 1. as1160 pin descriptions pin number pin name description see figure 2 din0:din9 data input. lvttl levels inputs. data on these pins are loaded into a 10-bit input register. tckr/fn transmit clock rising/f alling strobe select. lvttl level input. selects tclk active edge for strobing of d in x data. 1 = rising edge. 0 = falling edge. do+ + serial data output . non-inverting bus lvds differential output. do- - serial data output . inverting bus lvds differential output. den serial data ou tput enable. lvttl level input. if den is set to logic low the bus lvds outputs are in tri-state condition. pwdnn powerdown. lvttl level input. driving this pin low shuts down the pll, tri-states the outputs and puts the device into low power sleep mode. tclk transmit clock. lvttl level input. input for 20mhz to 66mhz system clock. sync1, sync2 synchronization. lvttl level input. assertion of sync (high) for at least 5 clock cycles to be transmit a synchronization si gnal (syncpat) on the bus lvds serial output. synchronization symbols continue to be sent if sync x continues to be asserted. sync1 and sync2 pins are combined through an or gate. dvdd +3.0v to +3.6v digital circuit power supply. this is the supply for all digital circuitry. dgnd digital circuit ground. gnd reference point for the digital part of the as1160. avdd +3.0v to +3.6v an alog power supply (pll and analog circuits) . avdd and dvdd should be at the same potential and must not be more than 0.3v apart even on transient basis. both supplys should be decoupled by a capacitor of typically 10nf. agnd analog ground (pll and analog circuits). tdi ieee 1149.1 test data input tdo ieee 1149.1 test data output tms ieee 1149.1 test mode select input tck ieee 1149.1 test clock input trstn ieee 1149.1 test reset input n/c no connection. leave open-circuit, do not connect these pins. a1 dgnd a2 n/c a3 din0 a4 sync1 a5 avdd a6 avdd a7 n/c b1 din1 b2 n/c b3 sync2 b4 avdd b5 agnd b6 agnd b7 avdd c1 din3 c2 dgnd c3 dvdd c4 dvdd c5 n/c c6 agnd c7 pwdnn d1 din5 d2 din2 d3 din4 d4 n/c d5 do- d6 den d7 do+ e1 din7 e2 din6 e3 tms e4 tclk e5 dvdd e6 dgnd e7 agnd f1 tdi f2 din8 f3 tck f4 din9 f5 dgnd f6 n/c f7 agnd g1 tdo g2 trstn g3 tckr/fn g4 dgnd g5 avdd g6 n/c g7 n/c
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 4 - 29 as1160/as1161 datasheet - pinout figure 3. as1161 pin assignments (top view) table 2. as1161 pin descriptions pin number pin name description see figure 3 rout0:rout9 data output. 4ma cmos level outputs. rckr/fn recovered clock rising/f alling strobe select. lvttl level input. selects rclk active edge for strobing of r out0 :r out9 data. 1 = rising edge. 0 = falling edge. refclk reference clock input. lvttl level input. input for 20mhz - 66mhz system clock. ri+ + serial data input. non-inverting bus lvds differential input. ri- - serial data input. inverting bus lvds differential input. pwdnn powerdown. lvttl level input. driving this pin low shuts down the pll, tri-states the outputs and puts the device into low power sleep mode. lockn lock. cmos level output. this signal goes low when the deserializer pll locks onto the embedded clock edge. rclk recovered clock. cmos level output. parallel data rate clock recovered from embedded clock. used to strobe r out0 :r out9 . ren output enable. lvttl level input. if ren is set to logic low r out0 :r out9 and rclk are in tri-state condition. dvdd +3.0v to +3.6v digital circuit power supply. this is the supply for all digital circuitry. dgnd digital circuit ground avdd +3.0v to +3.6v an alog power supply (pll and analog circuits) . avdd and dvdd should be at the same potential and must not be more than 0.3v apart even on transient basis. both supplys should be decoupled by a capacitor of typically 10nf. agnd analog ground (pll and analog circuits). tdi ieee 1149.1 test data input tdo ieee 1149.1 test data output tms ieee 1149.1 test mo de select input tck ieee 1149.1 test clock input trstn ieee 1149.1 test reset input n/c no connection. leave open-circuit, do not connect these pins. a1 dgnd a2 n/c a3 refclk a4 agnd a5 rout1 a6 dgnd a7 dvdd b1 avdd b2 agnd b3 rckr/fn b4 rout2 b5 dgnd b6 rout3 b7 dvdd c1 ri- c2 avdd c3 n/c c4 rout0 c5 dvdd c6 dvdd c7 rout4 d1 ren d2 ri+ d3 pwdnn d4 n/c d5 dvdd d6 rout5 d7 dgnd e1 lockn e2 rclk e3 n/c e4 dgnd e5 tck e6 trstn e7 dgnd f1 avdd f2 avdd f3 agnd f4 agnd f5 rout8 f6 tdi f7 rout6 g1 avdd g2 agnd g3 dgnd g4 rout9 g5 rout7 g6 tdo g7 tms
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 5 - 29 as1160/as1161 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only, and functional operation of the de vice at these or any other cond itions beyond those indicated in electrical character- istics on page 6 is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. table 3. absolute maximum ratings parameter min max units comments avdd, dvdd -0.3 +4 v lvcmos/lvttl input -0.3 v dd + 0.3 v lvcmos/lvttl output -0.3 v dd + 0.3 v bus lvds receiver input/output -0.3 +3.9 v bus lvds output short-circuit duration 10 ms power dissipation 1.47 w derate at 11.8mw/oc above 25oc ja 85 oc/w esd 2 kv hbm mil-std. 883e 3015.7 methods; operating temperature -40 +85 oc storage temperature -65 +150 oc junction temperature +150 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020d ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn).
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 6 - 29 as1160/as1161 datasheet - electrical characteristics 6 electrical characteristics av dd = dv dd = 3v to 3.6v, t amb = -40c to +85c, r load =28 , c load = 10pf, typical values @ t amb = +25c and v dd = 3.3v (unless otherwise specified). serializer electrical characteristics serializer timing requirements for tclk serializer switching characteristics table 4. electrical characteristics symbol parameter conditions min typ max unit serializer lvcmos/lvttl dc specifications (pins dinx, tclk, pwdnn, tckr/fn, sync1, sync2, den) v ih high level input voltage 2.0 v dd v v il low level input voltage gnd 0.8 v i in input current v in = 0v or 3.6v -1 +1 a serializer bus lvds dc specifications (pins do+ and do-) v od output differential voltage (do+ to do-) figure 34 on page 18 200 360 mv v od output differential voltage unbalance 1 35 mv v os offset voltage 1.1 1.2 1.3 v v os offset voltage unbalance 2 35 mv i os output short-circuit current do = 0v, din = high, pwdnn and den = v dd -13 -20 ma i oz tri-state output current pwdnn or den = gnd, do = 0v or v dd -1 +1 a i ox power-off output current pwdnn = den = v dd = 0v, do = 0v or 3.6v -1 +1 a serializer supply current (pins dvdd and avdd) i ccd serializer supply current (worst case) icc-pattern figure 16 on page 12 f = 20mhz 35 50 ma f = 66mhz 70 90 i ccxd serializer supply current (powerdown) pwdnn = gnd, f clk = dc (off) 400 700 a table 5. serializer timing requirements for tclk symbol parameter conditions min typ max unit f clk transmit clock freq. figure 20 on page 13 20 66 mhz t tcp transmit clock period 15.15 50 ns t tcdc transmit clock duty cycle 40 60 % t clkt tclk input transition time 3 6 ns t jit tclk input jitter 150 ps (rms) table 6. serializer switching characteristics 1 symbol parameter conditions min typ max unit t llht bus lvds low-to-high transition time figure 18 on page 13 0.25 0.4 ns t lhlt bus lvds high-to-low transition time 0.25 0.4 ns
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 7 - 29 as1160/as1161 datasheet - electrical characteristics deserializer electrical characteristics av dd = dv dd = 3v to 3.6v, t amb = -40c to +85c, r load =28 , c load = 15pf, receiver input range: 0v to 2.4v, typical values @ t amb = +25c and v dd = 3.3v (unless otherwise specified). t dis d in x setup to tclk time figure 21 on page 13 0ns t dih d in x hold from tclk time 4 ns t hzd do+, do- high-to- tri-state delay figure 22 on page 14 2 1.5 5 ns t lzd do+, do- low-to- tri-state delay 1.5 5 ns t zhd do+, do- tri-state-to- high delay 1.5 5 ns t zld do+, do- tri-state-to- low delay 1.5 5 ns t pwdl pwdnn minimum low time after v dd is in regulation figure 23 on page 14 50 s t spw sync pulse width figure 25 on page 15 5 x t tcp ns t pld serializer pll lock time figure 24 on page 14 400 x t tcp ns t sd serializer delay figure 26 on page 15 t tcp /2 t tcp /2 + 3 t tcp /2 + 5 ns t djit deterministic jitter (p-p) (worst case) icc-pattern figure 32 on page 18 f = 20mhz 150 300 ps (pp) f = 66mhz 50 100 ps (pp) t rjit random jitter (worst case) icc-pattern f = 20mhz 25 45 ps (rms) f = 66mhz 8 15 1. guaranteed by simulation and characterization. 2. because the serializer is in tri-stat e mode, the deserializer will lose pll lock and have to resynchronize before data transfer. table 7. electrical characteristics symbol parameter conditions min typ max unit deserializer bus lvds dc specifications (pins ri+ and ri-) v th differential threshold high voltage v cm = +1.2v +10 +75 mv v tl differential threshold low voltage -75 -20 i in input current v in = 2.4v, v dd = 3.6v or 0v -1 +1 a v in = 0v, v dd = 3.6v or 0v -1 +1 deserializer lvcmos/lvttl dc specifications (input pins pwdnn, rckr/fn, ren, refclk; output pins rout0:rout9, rclk, lockn) v ih high level input voltage 2.0 v dd v v il low level input voltage gnd 0.8 v i in input current v in = 0v or 3.6v -1 +1 a table 6. serializer switching characteristics 1 symbol parameter conditions min typ max unit
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 8 - 29 as1160/as1161 datasheet - electrical characteristics deserializer timing requirements for refclk deserializer switching characteristics i ilr input current, tms, tdi, trstn inputs v in = 0v -30 -60 a v oh high level output voltage i oh = -4 ma 2.2 3.0 v dd v v ol low level output voltage i oh = 4 ma gnd 0.25 0.5 v i os output short circuit current v out = 0v -15 -35 -60 ma i os output short circuit current, tdo output -80 -150 -220 ma i oz tri-state output current pwdnn or ren = 0v, v out = 0v or v dd -1 +1 a deserializer supply current (pins dvdd and avdd) i ccr deserializer supply current (worst case) figure 17 on page 12 f = 20mhz 45 60 ma f = 66mhz 100 130 i ccxr deserializer supply current (powerdown) pwdnn = 0v, ren = 0v 0.75 1.0 ma table 8. deserializer timing requirements for refclk symbol parameter conditions min typ max unit f rfclk refclk frequency 20 66 mhz t rfcp refclk period 15.15 t 50 ns t rfdc refclk duty cycle 30 50 70 % t rfcp/ t tcp refclk-to-tclk ratio 95 1 105 t rftt refclk transition time 3 6 ns table 9. deserializer switching characteristics 1 symbol parameter conditions pin/ frequency min typ max unit t rcp receiver out clock period t rcp = t tcp , figure 26 on page 15 rclk 15.15 50 ns t clh cmos/ttl low-to- high transition time figure 19 on page 13 rclk, r out x , lockn 1.5 4 ns t chl cmos/ttl high-to- low transition time 1.4 4 ns t dd deserializer delay, figure 27 on page 16 all temperatures, all frequencies 1.6 x t rcp + 1.0 1.75 x t rcp + 7.0 ns room temperature, 3.3v 20mhz 1.6 x t rcp + 2.0 1.6 x t rcp + 4.0 1.6 x t rcp + 6.0 room temperature, 3.3v 66mhz 1.75 x t rcp + 2.0 1.75 x t rcp + 4.0 1.75 x t rcp + 6.0 t ros r out data valid before rclk time figure 28 on page 16 20mhz 0.4 x t rcp 0.5 x t rcp ns 66mhz 0.38 x t rcp 0.5 x t rcp t roh r out data valid after rclk time figure 28 on page 16 20mhz -0.4 x t rcp 0.5 x t rcp ns 66mhz -0.38 x t rcp -0.5 x t rcp table 7. electrical characteristics (continued) symbol parameter conditions min typ max unit
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 9 - 29 as1160/as1161 datasheet - electrical characteristics scan circuitry timing requirements note: all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical quality control) methods. t rdc rclk duty cycle 45 50 55 ns t hzr high to tri-state delay figure 29 on page 16 r out x 36 ns t lzr low to tri-state delay r out x 36 ns t zhr tri-state to high delay r out x 46 ns t zlr tri-state to low delay r out x 46 ns t dsr1 2 deserializer pll lock time from pwdnn (with syncpat) figure 30 on page 17 , figure 31 on page 17 20mhz 5.2 7.5 s 66mhz 1.8 3 s t dsr2 2 deserializer pll lock time from syncpat 20mhz 5.1 7.5 s 66mhz 1.9 3 s t zhlk tri-state to high delay (powerup) lockn 4 12 ns t rclkl 1 rclk low time before lock achieved rclk 32xt rfcp ns t rnm 3 deserializer noise margin figure 33 on page 18 20mhz 0.8 1 ns 66mhz 200 300 ps 1. guaranteed by simulation and characterization. 2. for the purpose of specifying deserializer pll performance, t dsr1 and t dsr2 are specified with the refclk running and stable, and with specific conditions for the incoming data stream synchronization patterns (sync- pats). the derserializer should be initialized using either t dsr1 or t dsr2 . t dsr1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. syncpats should be sent to the devic e before initiating either condition. t dsr2 is the time required to indicate lock for the pow ered-up and enabled deserializer when the input (ri+ and ri-) conditions change from not receiving data to receiving syncpats. 3. t rnm is a measure of how much phase noise (jitter) the de serializer can tolerate in the incoming data stream before bit errors occur. the deserializer noise margin is guaranteed by design using statistical analysis. table 10. scan circuitry timing requirements symbol parameter conditions min typ max unit f tck tck clock frequency figure 15 on page 12 25 mhz t tck tck clock period 40 ns t s tck to tdi, tms setup time 2.0 ns t h tck to tdi, tms hold time 3.0 ns t wh, t wl tck pulse width, high or low 10.0 ns t wr trstn pulse width, low 2.5 ns t rec trstn-to-tck recovery time 2.0 ns t d tck to tdo delay 10 ns t z tck to tdo high z delay 10 ns table 9. deserializer switching characteristics 1 symbol parameter conditions pin/ frequency min typ max unit
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 10 - 29 as1160/as1161 datasheet - typical operating characteristics as1160 7 typical operating characteristics as1160 v dd = 3.6v, r load = 28 , c load = 10pf, t amb = +25oc (unless otherwise specified); figure 4. supply current vs supply voltage figure 5. power-down current vs supply voltage 0 10 20 30 40 50 60 70 80 90 2.8 3 3.2 3.4 3.6 3.8 supply voltage (v) supply current (ma) . fclk=20mhz fclk=66mhz 0 50 100 150 200 250 300 350 400 450 500 2.8 3 3.2 3.4 3.6 3.8 supply voltage (v) supply current (a) . figure 6. supply current vs clock frequency figure 7. supply current vs temperature 0 10 20 30 40 50 60 70 80 90 20 25 30 35 40 45 50 55 60 65 70 clock frequency (mhz) supply current (ma) . idd @ vdd=3,6v idd @ vdd=3v 0 10 20 30 40 50 60 70 80 90 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) supply current (ma) . fclk=20m hz fclk=66m hz figure 8. power-down current vs. temperature fi gure 9. deterministic jitter vs. temperature 200 300 400 500 600 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) supply current (a) . 0 40 80 120 160 200 240 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) deterministic jitter (pk-pk) (ps) .
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 11 - 29 as1160/as1161 datasheet - typical operating characteristics as1161 8 typical operating characteristics as1161 v dd = 3.6v, c load = 15pf , t amb = +25oc (unless otherwise specified); figure 10. supply current vs supply voltage figure 11. power-down current vs supply voltage 0 10 20 30 40 50 60 70 80 90 100 110 120 2.8 3 3.2 3.4 3.6 3.8 supply voltage (v) supply current (ma) . fclk=20mhz fclk=66mhz 500 550 600 650 700 750 800 850 900 950 1000 2.8 3 3.2 3.4 3.6 3.8 supply voltage (v) supply current (a) . figure 12. supply current vs clock frequency figure 13. supply current vs temperature 20 30 40 50 60 70 80 90 100 110 120 20 25 30 35 40 45 50 55 60 65 70 clock frequency (mhz) supply current (ma) . idd @ vdd=3,6v idd @ vdd=3v 20 30 40 50 60 70 80 90 100 110 120 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) supply current (ma) . fclk=20mhz fclk=66mhz figure 14. power-down current vs. temperature 500 600 700 800 900 1000 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) supply current (a) .
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 12 - 29 as1160/as1161 datasheet - timing diagrams 9 timing diagrams figure 15. jtag timing diagram figure 16. worst-case serializer icc test pattern figure 17. worst-case dese rializer icc test pattern t tck tdi, tms tck t wh t wl t spw t spw t d t y t rec t wr tdo trstn tclk odd d in even d in rclk odd r out even r out
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 13 - 29 as1160/as1161 datasheet - timing diagrams figure 18. serializer bus lvds output load and transition times figure 19. deserializer cmos/ttl output load and transition times figure 20. serializer input clock transition time figure 21. serializer setup and hold times t llht t lhlt v diff 20% 80% 20% 80% v diff = 0v r load do+ do- 10pf 10pf v diff = do+ - do- 28 t clh 20% 80% 20% 80% deserializer 15pf cmos/ttl output t chl t clkt tclk 10% 90% 10% 90% 3v 0v t clkt 1.5v 1.5v 1.5v t tcp t dis t dih 1.5v setup 1.5v hold tclk d in0:9 timing shown for tckr/fn is low
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 14 - 29 as1160/as1161 datasheet - timing diagrams figure 22. serializer tri-state test circuit and timing figure 23. serializer power up timing figure 24. serializer pll lock time and pwdnn tri-state delays t zhd t zld t lzd t hzd 1.5v 1.5v 50% 50% do+ v ol v oh 50% 50% den 3v 0v den r load do+ do- 10pf 10pf 28 do- vdd pwdnn tpwdl 2.0v 0.8v t hzd or t lzd t zhd or t zld <400 cycles t pld do+ do- pwdnn tclk tri-state tri-state output active . . . . . .
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 15 - 29 as1160/as1161 datasheet - timing diagrams figure 25. sync timing delays figure 26. serializer delay ren t spw t spw minimum timing met data syncpat syncpat data do+ do- sync1 or sync2 tclk sync1 or sync2 pwdnn tclk do+ do- 11111 00000 syncpat syncpat t sd timing shown for tckr/fn = high start bit start bit stop bit stop bit d in0:9 symbol n + 1 d in0:9 symbol n d out0:9 symbol n - 1 d out0:9 symbol n tclk d in do- do+ 0 1 2 9 8 d in0:9 symbol n + 2 t tcp start bit d out0:9 symbol n + 1 0 1 2 9 8 0 1 2
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 16 - 29 as1160/as1161 datasheet - timing diagrams figure 27. deserializer delay figure 28. deserializer data valid out times figure 29. deserializer tri-state test circuit and timing diagram start bit stop bit start bit d in0:9 symbol n + 1 d in0:9 symbol n d in0:9 symbol n + 1 t dd 1.3v 1.1v rclk r out r out 0:9 symbol n - 1 r out 0:9 symbol r out 0:9 symbol n + 1 start bit stop bit stop bit r- r+ 1.5v 1.5v t high t low t high t low t roh t ros data valid before rclk rclk rckr/fn = low rclk rckr/fn = high r out0:9 data valid after rclk 50 500 450 +7v lz, zl open hz, zh oscope t zlr t lzr t zhr t hzr v ol v oh v ol v oh v ol + 0.5v v oh - 0.5v v oh - 0.5v v ol + 0.5v 1.5v 1.5v ren
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 17 - 29 as1160/as1161 datasheet - timing diagrams figure 30. deserializer pll lock times and pwdnn tri-state delays figure 31. deserializer pll lock time from syncpat 2.0v data pwdnn refclk ri+ ri- t dsr1 0.8v don?t care tri-state tri-state tri-state tri-state tri-state tri-state syncpats lockn r out0:9 rclk ren t zhlk t zhr or t zlr t hzr or t lzr sync symbol or d in0:9 rckr/fn = low t rclkl ren tri-state tri-state rclk tri-state tri-state r out0:9 sync symbol or d in0:9 t zhr or t zlr t hzr or t lzr tri-state lockn refclk ri+ ri- pwdnn data syncpats t dsr2 0.8v 1.3v 1.1v don?t care 1.2v t rclkl
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 18 - 29 as1160/as1161 datasheet - timing diagrams figure 32. definition of deterministic jitter (t djit ) figure 33. receiver bus lvds input skew margin where: t sw is the setup and hold time (internal data sampling window). t djit is the serializer output bit position jit ter as a result of jitter on tclk. t rnm is the receiver noise time margin. figure 34. data transfer mode, v od diagram (v od = do+ - do-) t djit(p-p) 0 differential (do+) - (do-) waveform superimposed icc pattern trigger t rnm 1.2v ri- ri+ v th v tl 1.0v t sw ideal sampling position t djit t rnm t djit as1160 tclk din0:9 do- do+ r load parallel to serial 10
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 19 - 29 as1160/as1161 datasheet - detailed description 10 detailed description the serializer/deserializer chipset transfers 10 parallel lvttl data bits over a serial bus lvds link up to 660mbps at clock speeds from 20mhz to 66mhz. for the serializer, an on-board pll serializes the input data an d inserts two control bits (start & stop bit) into the data stream. the deserializer uses a separate reference clock (refclk) and an onboard pll to extract the clock information from the incoming data stream and then deserialize the data. the deserializer monitors the incoming clock information, determines lock status and asserts the lockn output high when loss of lock occurs. note: the chipset is also capable of driving data over unshielded twisted pair cable. the chipset has three active states of operation: - initialization - data transfer - resynchronization the chipset also has two passive states: - powerdown - tri-state note: there are also test modes fo r jtag access and at -speed bist (built-in-self-test). initialization initialization of both devices must occur before data transmissi on begins. initialization refers to synchronization of the serializer and deserializer plls to loca l clocks, which may be the same or separa te. afterwards, synch ronization of the deserializer to the serializer occurs. 1. when v dd is applied and reaches a stable value between +3.0v and +3.6v, the pwdnn of the serializer has to stay low for at least 50s to ensure proper operation (see figure 23 on page 14) , the respective output enter tri-state. after pwdnn is high the pll in the serializer begins locking to a local clock. when v dd is applied to the deserializer, the respective outpu ts enter tri-state and an on-chip power-on circuitry disables internal circuitry. when v dd reaches v ddok (2.5v) the pll in the deserializer begins locking to a local clock. for the serializer, the local clock is the transm ited clock (tclk) provided by the source asic or other device. for the deserializer, a local clock must be applied to pin refclk that can be provided by any source. the serializer outputs remain in tri- state while the pll locks to the tclk. after locking to tclk, the serializer is now ready to send data or syncpats (sync pattern s), depending on the levels of the sync1 and sync2 inputs or a data stream. the syncpat sent by the serializer consists of six ones and six zeros switching at the input clock rate. note that the deseri alizer lockn output wi ll remain high while its pll locks to the incoming data or to syncpats on the input. 2. the deserializer pll must synchronize to the serializer to complete initialization. the deserializer will lock to non-repetitive data patterns. however, the transmission of syncpats enables the deserializer to lock to the serializer signal within a specified time (see figure 24 on page 14) . the application determines control of pins sync1 and sync2. a direct feedback loop from the lockn pin is mandatory (see figure 36 on page 23) . in all cases the serializer stops sending syncpats after both sync inputs return low. when the deserializer detects edge tr ansitions at the bus lvds input, it will attempt to lock to the embedded clock information. when the deserializ er locks to the bus lvds clock, th e lockn output w ill go low. when lockn is low, the deserializer outputs represent incoming bus lvds data.
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 20 - 29 as1160/as1161 datasheet - detailed description data transfer after initialization, the serializer will accept data from inpu ts din0:din9. the serializer uses tclk to latch incoming data. tckr/fn selects which edge the serializer uses to st robe incoming data. tckr/fn high selects the rising edge for clocking data and low selects the falling edge. if sync1 or sync2 is high for more than 5 tclk cycles, the data at din0:din9 is ignored regardless of clock edge. after determining which clock edge to use a start and stop bit, appended internally, frame the data bits in the register. the start bit is always high and the stop bit is always low. in the serial stream the star t and stop bits are used as the embedded clock bits. the serializer transmits serialized data and clock bits (10 + 2 bits) from the serial data output (do+ and do-) at 12 times the tclk frequency. for example, if tclk is 66mhz, the serial rate is 66 x 12 = 792 mega bits per second. since only 10 bits are from input data, the serial payload rate is 10 times the tclk frequency (if tclk = 66mhz, the payload data rate is 66 x 10 = 660mbps). the data source provides tclk and must be in the range of 20mhz to 66mhz nominal. the serializer outputs (do+ and do-) c an drive a point-to-point connection (see figure 37 on page 24) or a multidrop configuration (see figure 35) . in a multidrop configuration one serializer is connected through a backplane bus with limited multiple deserializers. the outputs transmit data when den, pwdnn are high and sync1, sync2 are low. note: when den is driven low, the serializer output pins will enter tri-state. figure 35. multidrop configuration when the deserializer synchronizes to the serializer, pin lockn is low. the deserializer locks to the internal clock and uses it to recover the serialized data. r out0 :r out9 data is valid when lockn is low, otherwise r out0 :r out9 is invalid. pins r out0 :r out9 use pin rclk as the reference to data. the pol arity of the rclk edge is controlled by the rckr/ fn input (see figure 28 on page 16) . r out0 :r out9 , lockn and rclk outputs will drive a maximum of three cmos input gates (15pf load) with a 66mhz clock. as1160 asic asic asic asic asic as1161 as1161 as1161 as1161 56 56 10-bit 10-bit 10-bit 10-bit 10-bit r x r x r x r x transmitter
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 21 - 29 as1160/as1161 datasheet - detailed description resynchronization when the deserializer pll locks to the embedded clock edge, th e deserializer lockn pin asserts a low. if the deseri- alizer loses lock, pin lockn output will go high a nd the outputs (including rcl k) will enter tri-state. the user?s system monitors the pin lockn to detect a lo ss of synchronization. upon detection, the system can arrange to pulse the serializer sy nc1 or sync2 pin to resynchronize. multiple resynchronization approaches are possible. it is mandatory to provide a feedback loop using pin lockn to control the sync request of the serializ er (sync1 or sync2). two sync pins ar e provided for multiple control in a multi-drop application. sending syncpats for resynchronizati on is desirable when lock times within a specific time are critical. powerdown the low-power powerdown mode can be used while no data tran sfer is taking place. the serializer and deserializer use the powerdown mode to reduce power consumption by: - the deserializer enters powerdown when pins pwdnn and ren are low. - the serializer enters powerdown when pin pwdnn is driven low. in powerdown, the pll stops and the outp uts enter tri-state, which disables load current and reduces supply current to the a range. note: to exit powerdown, drive pin pwdnn high. before valid data exchanges between the serializer and des erializer, the devices must re-initialized and resynchro- nized to each other. init ialization of the serializer ta kes a maximum of 400 tclk cycles . the deserializer will initialize and assert lockn high until lock to the bus lvds clock occurs. tri-state the serializer enters tri-state when pin den is driven low. this puts both driver output pins (do+ and do-) into tri- state. when den is driven high, the serializer returns to th e previous state, as long as all other control pins remain static (sync1, sync2, pwdnn, tckr/fn). when pin ren is driven low, the deserializer enters tri-state. consequently, the receiver output pins (r out0 :r out9 ) and rclk will enter tri-state. the lockn output re mains active, reflecting the state of the pll.
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 22 - 29 as1160/as1161 datasheet - application information 11 application information power considerations an all cmos design of the serializer and deserializer ma kes them inherently low power devices. in addition, the con- stant current source nature of the bus lvds outputs minimizes the slope of the speed vs. i dd curve of conventional cmos designs. the pins avdd and dvdd should be bypassed with a 100nf and a 1nf ceramic capacitor in parallel. the 1nf capac- itor should be closest to the pin. powering up the deserializer the as1161 can be powered up at any time by following a proper sequence. the refclk input can be running before the deserializer powers up and it must be running in order fo r the deserializer to lock to incoming data. the deserializer outputs will remain in tri-state until the deserializer detects data transmission at its inputs and locks to the incoming data stream. transmitting data once the serializer (as1160) and deserializer (as1161) are powered up, they must be phase locked to each other to transmit data. phase locking occurs when th e deserializer locks to incoming data or when the serializer sends patterns. the serializer sends syncpats whenever the sync1 or sy nc2 inputs are high. the lockn output of the deserial- izer remains high until it has locked to the incoming data stream. connecting the lockn ou tput of the deserializer to one of the sync inputs of the serializer will guarantee t hat enough syncpats are sent to achieve deserializer lock (see figure 36 on page 23) . as long as the deserializer lockn output is low, valid data is presented at the deserializer outputs (r out0 :r out9 ), except for the specific case of loss of lock during transmission (see lock loss recovery on page 23) . table 11. deserializer truth table inputs outputs pwdnn ren lockn r out x rclk high high high (not locked) z z high high low (not locked) active 1 1. active indicates the rclk will be running if the deserial izer is locked. the timing of rclk with respect to rout0:rout9 is determined by rckr /fn. rout0:rout9 and rclk are tri- stated when lockn is asserted high. active 1 low x (dont care) z z z high low active 2 2. active indicates the lockn output will reflect the stat e of the deserializer with regard to the selected data stream. zz
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 23 - 29 as1160/as1161 datasheet - application information figure 36. typical application noise margin the deserializer (as1161) noise margin is the amount of input jitter (phase noise) that the deserializer can tolerate and still reliably receive data. various environ mental and systematic factors include: - serializer: tclk jitter, v dd noise (noise bandwidth and out-of-band noise) - media: isi (inter symbolic in terference), large vcm shifts - deserializer: v dd noise lock loss recovery in the case where the deserializer (as1161) loses lock during data transmission, up to 3 cycles of data that were previ- ously received can be invalid. this is due to the delay in the lock detection circuit. the lock detect circuit requires that invalid clock information be received 4 times in a row to indica te loss of lock. since clock information has been lost, it is possible that data was also lost during these cycles. therefore, after the deserializ er re-locks to the incoming data stream and the deserializer lockn pin goes low, at least th ree previous data cycles should be suspect for bit errors. the deserializer can re-lock to the incoming data stream by making the serializer re-send syncpats. hot insertion as all blvds devices the as1161 is hot pluggable but you have to follow some rules. hot insertion should be performed with pins making contact in the following order: - ground pins -v dd pins - i/o pins note: when removing the device, the pin groups should be removed in reverse order from insertion. as1160 do+ do- tclk tckr/fn input latch pll din0:9 parallel -to- serial 10 timing & control den sync1 sync2 as1161 ri+ ri- output latch pll rout0:9 10 timing & control refclk ren lockn rclk rckr/ parallel -to- serial jtag jtag 56 pwdnn pwdnn asic/ fpga/ dsp asic/ fpga/ dsp v dd v dd clock recovery
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 24 - 29 as1160/as1161 datasheet - application information pcb considerations the serializer and deserializer should be placed as close to the pcb edge connector as possible. in multiple deserial- izer applications, the distance from the deserializer to the sl ot connector appears as a stub to the serializer driving the backplane traces. longer stubs lower the impedance of the bu s, increase the load on the serializer and lower the threshold margin at the deserializers. deserializer devices should be placed much less than one inch from slot connec- tors. because transition times are very fast on the serializer bus lvds outputs, reducing st ub lengths as much as pos- sible is the best method to ensure signal integrity. for bus lvds applications the lvttl, lvcmos and bus lv ds signals should be separated from each other to pre- vent coupling into the bus lines. this can be achieved by using a four-layer pcb where the power, ground and input/ output signals are separated. transmission media the transmission line characteristics affect the performa nce of the as1160/as1161. it?s recommended to use con- trolled-impedance media and to terminate at both ends of the transmission line (see figure 37) . twisted pair cables should be used due to their superior signal quality and the less emi generation. noise which is picked up as common mode in the twisted pair is reje cted by the differential receiver. it?s important to eliminate reflections and to run the differ ential traces as close together as possible to ensure that the noise is coupled as common mode. also take care of matchi ng the electrical length of the traces to prevent a degrada- tion of the magnetic field cancellation. to avoid an external magnetic field, the differential output signals should also be placed as close together as possible. the potential of offsetting the ground leve ls of the serializer vs. the deserializ er must be considered. the bus lvds provides a +1.2v common mode range at the receiver inputs. figure 37. double-terminated point-to-point the serializer/deserializer chipset can be used in many different topologies. such as multidrop configurations (see fig- ure 35 on page 20) , through a pcb trace or th rough twisted pair cable (see figure 37) . in point-to-point configurations, it?s possible to terminated the transmission line only once at the receiver end. with only one termination the reflections and the differential signa l swing are larger compared to a double termination. parallel data out parallel data in serialized data 56 56 as1160 as1161 strip line or twisted pair z = 28 do- do+ ri- ri+ 10-bit 10-bit
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 25 - 29 as1160/as1161 datasheet - application information failsafe biasing the as1161 has an input threshold sensitivity of 75mv, which allows a greater differential noise margin. however, in cases where the receiver input is not being ac tively driven, the increased sensitivity of the as1161 can pickup noise as a signal and cause unintentional locki ng (e.g., when the input cable is left floating). figure 38. failsafe biasing setup external resistors can be added to the receiver circuit to prevent noise pickup as shown in figure 38 . in such circuits, the non-inverting receiver input is pulled up and the invertin g receiver input is pulled down by high value resistors. the pull-up and pull-down resistors (r 1 and r 2 in figure 38 ) provide a current path through the termination resistor (r load ) which biases the receiver inputs when they are not connected to an active driver. note: the value of the pull-up and pull-down re sistors should be chosen so that suff icient current is drawn to provide a +15mv drop across the termination resistor. signal integrity for a validation of the signal qualitiy in an a pplication or in a simulation, the parameters t djit and t rnm can be used to generate an eye pattern mask. t djit measures the transmitter?s ability to place data bits in the ideal position to be sampled by the receiver. the typical t djit parameter of 50ps @ 66mhz indicates that the crossing point of the tx data is 50ps before the ideal crossing point. the t djitmin and t djitmax parameters specify the earliest and latest time that a crossing will occur relative to the ideal position. figure 39. eye pattern mask generation and signal quality validation first of all, t rnm is calculated by measuring how much of the bit t he receiver needs to ensure correct sampling. this calculated amount is subtracted from the i deal bit and what?s left of it is availa ble for external sources of noise and is called t rnm . it is the offset from t djit for the test mask within the eye opening. the vertical limits of the mask are determined by the as1161 receiver input threshold of 75mv. r 1 r 2 r load v dd y1 y2 x1 x2 t djit (min) t djit (typ) t djit (max) t rnm ideal crossing vertical = 200mv/div horizontal = 200ps/div
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 26 - 29 as1160/as1161 datasheet - application information jtag test modes instructions supported by the as1160/as1161 and it s respective operational binary codes are shown in table 12 . note: boundary scan description language (bsdl) model file s for the as1160 and the as1161 are available on the internet. sample/preload this is a mandatory instruction for the ieee 1149.1 specification that supports two functions. the digital i/os of the device can be sampled at the boundary scan test data regi ster without interfering with the normal operation of the device. sample/preload also allows the device to shift data into the boundary scantest data register through tdi. bypass when the bypass instruction is latched into the instructi on register, tdi connects to tdo through the 1-bit bypass test data register. this allows data to pass from td i to tdo without affecting the device?s normal operation. extest implemented at lvds levels as a go/no-go test (e.g. missing cables). idcode the as1160/as1161 id code is provided to the tdo output. runbist an at-system-speed interconnect test instruction. it is executed in approximately 33ms (@ 66mhz system speed). there are two bits in the rx bist data register for no tification of pass/fail and t est_complete. pass indicates that the ber (bit-error-ra te) is better than 10 -7 . if both the as1160 and the as1161 have loaded the runbist in struction into their instruct ion registers, both devices must move into the rti state within 4k system clocks (at a sclk of 66mhz and tck of 1mhz this allows for 66 tck cycles). this is only an issue when both devices are not on the same scan chain or lsp, although, it can be a problem with some multi-drop devices. table 12. instruction codes instruction code sample/preload 0101 bypass 1111 extest 0001 idcode 1010 runbist 1110 table 13. 32bit id code msb lsb device version (4bits) device id (16bits) manufacturer id (11bits) fixed value (1bit) as1160 0100 0001000101100000 01011011010 1 as1161 0100 0001000101100001 01011011010 1
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 27 - 29 as1160/as1161 datasheet - package drawings and markings 12 package drawings and markings the device is available in an ctbga 49-bumps package. figure 40. ctbga 49-bumps package 32 5 1 4 6 7 0 0 8 0 b 0 0 0 0 m m
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 28 - 29 as1160/as1161 datasheet - ordering information 13 ordering information the devices are available as the standard products shown in table 14 . note: all products are rohs compliant and pb-free. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.a ustriamicrosystems.com/distributor table 14. ordering information ordering code description delivery form package as1160-bctt serializer tape and reel ctbga 49-bumps AS1161-BCTT deserializer tape and reel ctbga 49-bumps
www.austriamicrosystems.com/interfaces-lvds/as1160_61 revision 1.01 29 - 29 as1160/as1161 datasheet copyrights copyright ? 1997-200 9, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaet ten, austria-europe. trademarks registered ?. all rights reserved. the mate rial herein may not be reproduced, adapted, merged, translated, stored, or used wit hout the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freed om of the described devices from patent infringement. austriamicrosystems ag reserves the right to change spec ifications and prices at an y time and without notice. therefore, prior to designing this pro duct into a system, it is necessary to check with austriam icrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unus ual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the m anufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to reci pient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors a nd representatives, please visit: http://www.austriamicrosystems.com/contact

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